Field of the Invention
The present invention relates to a direct memory access (DMA) system for data transfer in a communication apparatus for example.
Related Background Art
In a conventional DMA transfer in a communication apparatus for example, various parameters are set at a DMA controller (DMAC) under the control of a CPU such as a microprocessor, and upon instruction of starting a DMA transfer, data are transferred between a transmitter/receiver buffer and a memory. Particularly, upon reception of one word communication data for example, a DMA data transfer request is issued for transferring data from the reception buffer to the memory. The DMAC then requests to use the system bus to and cause for transferring the received one word data to the memory by means of, for example, a cycle steal method. By repeating such DMA transfer operation, communication data of plural words are transferred to the memory. After completion of transferring communication data of one frame length, an end of one frame reception is notified to the CPU which resets various parameters of the DMAC for preparation of receiving the next frame.
Accordingly, it becomes necessary for the CPU to execute at least the following steps during the time from the one frame reception end to the next frame reception start.
Step 1: task change after responding to interruption PA1 Step 2: secure memory areas for receiving next frame PA1 Step 3: resetting internal registers of DMAC
However, since these steps are executed under program control, it takes much time. Particularly at step 2, it becomes necessary to use an additional task for supervising the memory areas themselves. This means that a sufficient marginal time must be given to the overall operation of steps 1 to 3 in designing the communication system. Thus, the reception capability of the communication system, i.e., the capability of reliably receiving and processing high speed consecutive frames, has been restricted in some degree.